315MHz / 434MH based on MC33591 / MC33592

Abstract: A 315MHz / 434MHz OOK / FSK receiving circuit designed based on MC33591 / MC33592 is given. The data rate of this circuit is 1 ～ 11kbaud, the sensitivity of OOK / FSK is -105dBm, the fastest wake-up time is 1ms, and the power supply voltage is ： VGND-0.3 ～ 5.5V, the power supply current in running and configuration mode is 7.4mA, and the current consumption in standby mode is 250μA. In addition, the receiving circuit also has a three-wire SPI interface, which can directly interface with the microcontroller.

The MC33591 / MC33592 is a monolithic integrated receiver. The chip contains a 660kHz mid-band pass filter, a complete VCO, a mixer that can eliminate images, a Manchester coded clock regeneration circuit, and a complete SPI interface. It can be used to design 315MHz / 434MHz OOOK / FSK receiving circuit.

1 MC33591 / MC33592 pin functions

MC33591 uses LQFP24 package, its pin arrangement is shown in Figure 1, and the functions of each pin are listed in Table 1.

Table 1 MC33591 / MC33592 pin function description

2 Internal structure and working principle

The radio frequency part of MC33591 / MC33592 is composed of a mixer capable of eliminating image interference, an intermediate band pass filter of 660 kHz, an automatic gain control stage and an OOK / FSK demodulator. The control part includes data manager, configuration register, serial interface, state controller and so on. Its SPI interface can be used to program the modulation mode. The data of the circuit can be output from the comparator or from the SPI port when the data manager is enabled.

2.1 Local oscillator

Since the PLL loop filter has been integrated in the IC, the component values ​​in actual application can be slightly improved by an external filter at the PFD pin according to the local oscillator parameters. The user can select the best working condition by adding an external filter. The gain of the phase-locked loop circuit can be programmed by the PG bit. When this position is 1, the loop is in a low gain state.

2.2 Communication protocol

When communicating with MC33591 / MC33592, the duty cycle of the data after Manchester encoding: 48% ~ 52% in OOK mode, and 45% ~ 55% in FSK mode. In addition, the communication protocol code also includes preamble (ID), ID (identification), header (Hearder) words and data, etc. The content of ID (recognition) word is coded according to Manchester, and is pre-loaded into the configuration register 2 in the circuit. The transmission rate of the identification word is consistent with the numerical transmission rate.

In order to be different from identification or header word encoding, the content of the preamble must be carefully defined.

The header word should be the 4-bit Manchester code "01010" or its complement.

General data (Data) should follow the header without any delay. The data is ended by a message end command? End-of-Message OEM ?, EOM consists of 2 NRZ continuous 1 or 0. When FSK modulation is used, the data is terminated by an EOM and cannot be simply terminated by the RF signal.

Figure 2 shows a complete signal with preamble word, identification word, header word followed by 2 data bits and end word. The preamble is usually placed before the two words of identification and header.

Figure 3 is a schematic diagram of a complete signal using ID detection. When the receiver enters the standby mode, the required setup time is usually 1ms.

2.3 Data Manager

The data manager function module has five purposes, which are ID (identification) word detection, header identification, clock regeneration, data output and clock regeneration on the SPI channel, and end of information detection.

2.4 Serial interface

The receiver (ROMEO2) and the microcontroller generally communicate through a serial external interface SPI (Serial Peripheral Interface). If the SPI interface is not used, the reset terminal PORT? Power On Reset? Will set the receiver to the default structure to complete the correct operation. The SPI interface operates through the following three input / output terminals:

(1) Serial clock SCLK;

(2) Main control output controlled input MOS;

(3) Main control input controlled output MIS.

The master set clock synchronizes the data input / output through MOS and MIS. The master and slave devices can exchange one byte of information within 8 clock cycles. During operation, the master device generates the SCLK clock and inputs it to the slave device. MOS is configured as an input in the master device and as an output line in the slave device; when the MIS line of the master device is configured as an output, it is used as an input line in the slave device.

MIS and MOS lines generally transmit serial data in one direction, and the highest bit is sent first. The data is valid on the falling edge of SCLK and moves on the rising edge of SCLK. When there is no data output, SCLK and MOS are forced to low level. When using the microcontroller of Motorola, its clock phase and polarity control bit SPI must be set to CPOL = 0 and CPHA = 1.

2.5 Configuration register

In the configuration mode, as long as the reset terminal (RESETB) maintains a low level for a long time, the microcontroller will act as the main device to provide the clock signal on the SCLK and provide control and configuration bits on the MOS line. If the default configuration is not used, the microcontroller (MCU) will change the configuration by writing the configuration word to the configuration register. The contents of the configuration register can be returned to the microcontroller and tested.

When the RESETB pin is high, if the data manager is enabled (DME = 1), the receiver will act as the main device to send the received data on the MOS line, and at the same time send the received clock signal on SCLK.

image 3

When the receiver SPI changes from the master setting (working mode) to the slave setting (configuration mode) or from the slave setting to the master setting, it is recommended that the SPI in the MCU be set to the slave setting before mode conversion.

When the power is turned on, por first resets the internal registers so that the receiver system is set in the default mode. In this configuration, SPI is disabled, and the receiver will send the original data on the MOSI line. In fact, the default configuration allows the circuit to operate as an independent receiver without external control.

The MC33591 / MC33592 has three configuration registers CR1 ~ CR3. Among them, the configuration register 1 (CR1) controls the access (read or write) of the three registers. It is mainly used to select the carrier frequency, set the data modulation method, control the strobe oscillator enable, define the strobe ratio, and control the data manager Yes, define header words, etc. Configuration register 2 (CR2) is used to define the content of the recognition word. Configuration register 3 (CR3) is used to define the data rate, set the mixer gain, control the conversion of the MIXOUT pin, and set the phase comparator gain.

2.6 Receiver mode

After power-on reset, the receiver generally has three different modes, the first is the sleep mode, which is the low power mode. The second is the configuration mode, which is used to read and write internal registers. In this mode, the SPI is in the slave position and the receiver is enabled. The crystal oscillator oscillates to generate the clock signal for SPI. The demodulated data can be read by DMAT, but cannot be sent through SPI. The third is the working mode. When in this mode, the receiver can wait for radio frequency signals or receive information.

3 The application circuit of MC33591 / 592

The application circuit of MC33591 / MC33592 is shown in Figure 4. The circuit should select 9.864375MHz crystal oscillator at 315MHz, and 13.58065MHz crystal oscillator at 434MHz. When FSK modulation is used, the relationship between the value of the low-pass filter capacitor C2 in Figure 4 and the data rate is listed in Table 2.

Table 2 The relationship between C2 and data rate when using FSK modulation

Liquid Crystal Display For Clock

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