In February 2002, the US Federal Communications Commission (FCC) allocated a significant portion of the spectrum—specifically from 3.1 to 10.6 GHz—for ultra-wideband (UWB) wireless communication systems, sparking a global surge in research and development. UWB technology offers several advantages, such as low power consumption, high data transmission rates, and strong resistance to interference, making it ideal for various applications ranging from radar systems to high-speed wireless networks.
The ultra-wideband low noise amplifier (LNA) is a critical component in the front-end of a UWB wireless receiver. It plays a vital role in determining the system's overall performance, including bandwidth, noise figure, and power consumption. This paper presents a CMOS-based LNA designed for operation in the 3–5 GHz frequency range. The design process starts with selecting an appropriate LNA structure, followed by detailed circuit analysis, simulation, and finally, a comprehensive evaluation of the results.
When designing broadband LNAs, traditional approaches often use distributed or balanced amplifier techniques. However, these methods typically require significant DC power, which makes them unsuitable for UWB systems that demand energy efficiency. Instead, modern designs incorporate band-pass filter input matching and parallel resistance negative feedback structures. The former allows for a wide bandwidth and flat gain response, while the latter enhances the frequency range by reducing the input quality factor. Additionally, noise cancellation techniques are applied to further improve the noise figure.
Figure 1 shows the schematic of the proposed LNA circuit. It features a parallel negative feedback Cascode structure, along with on-chip DC blocking capacitors (C1, C2, C3), a feedback resistor (Rf), and a DC blocking capacitor (Cf). Input matching networks (Lg, L1) help achieve proper impedance matching for the narrowband LNA. Transistors M1 and M2 form the main amplification stage, with M1 acting as a common-source amplifier and M2 as a common-gate amplifier to enhance reverse isolation and reduce the Miller effect. A low-Q load is formed using L2, Rd, and Cd to extend the output bandwidth. M3 and M4 act as a source follower in the output stage, and together with M1 and M2, they create a feedforward noise cancellation structure.
For the broadband input matching analysis, the output buffer M3 is removed. The transconductance stage formed by M1, M2, and L1 is modeled as a transconductance Gm. Using this model, the small signal equivalent circuit is derived, allowing for the calculation of the input impedance (Zin). Through MATLAB simulations, it was found that Zin closely matches 50Ω across the 3–5 GHz band, confirming successful broadband input matching.
Gain analysis involves deriving the expression for the main amplifier gain (Amain(s)). By adjusting parameters like transconductance (Gm) and load impedance (ZL), the gain can be optimized. An inductor (L3) is added in series with the gate of the output buffer (M3) to boost the gain. Simulations show that this configuration improves the maximum gain from 15 dB to 18 dB, aligning with theoretical predictions.
Noise cancellation is achieved through the use of feedback loops and carefully designed transistors. The noise current (Ini) from the Cascode structure is processed through feedback paths and amplified by different stages. By combining the outputs of inverting and non-inverting amplifiers, the noise at the output is reduced without affecting the input signal. Simulations confirm that increasing the inductance (L4) improves high-frequency noise performance.
The LNA was simulated using the SMIC 0.18-μm RF CMOS process with a 1.8 V supply voltage. The core circuit and output buffer consume 9 mA and 5 mA respectively, resulting in a total power consumption of approximately 20.5 mW. Simulation results show good input and output matching, acceptable reverse isolation, and improved gain and noise performance. The third-order intercept point (IIP3) reaches -12.9 dBm at 4.5 GHz, demonstrating strong linearity.
In conclusion, this paper presents a CMOS-based ultra-wideband LNA operating in the 3–5 GHz band. The design includes detailed analysis of input matching, gain, and noise cancellation techniques. The simulation results confirm that the amplifier meets the requirements for UWB systems, making it suitable for future high-speed wireless applications.
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