In February 2002, the U.S. Federal Communications Commission (FCC) allocated the spectrum range of 3.1 to 10.6 GHz for ultra-wideband (UWB) wireless communication systems, sparking a global surge in research and development. Ultra-wideband technology is known for its low power consumption, high data transmission rates, and strong resistance to interference. As a critical component in UWB receiver front-end systems, the low noise amplifier (LNA) plays a key role in determining the system’s bandwidth, noise performance, and power consumption. This paper presents a CMOS-based LNA designed for UWB applications operating in the 3 to 5 GHz frequency range. The design process starts with selecting an appropriate LNA structure, followed by circuit analysis, simulation, and finally, the interpretation of the simulation results.
For broadband LNAs, traditional techniques such as distributed and balanced amplifiers are commonly used. However, these approaches often require significant DC power consumption, making them unsuitable for UWB systems. In contrast, modern designs employ band-pass filter input matching or parallel resistance negative feedback structures. The former offers a wide bandwidth and good noise performance but requires a higher-order bandpass filter at the input. The latter expands the bandwidth by introducing a resistive feedback loop that reduces the input quality factor. To further improve noise performance, noise cancellation techniques are applied. Figure 1 shows the schematic of the circuit structure used in this design.
In Figure 1, the main amplification section consists of a parallel negative feedback Cascode structure. Capacitors C1, C2, and C3 are on-chip DC blocking capacitors, while Rf is the feedback resistor and Cf blocks DC in the feedback loop. Inductors Lg and L1 are part of the input matching network for narrowband LNAs. M1 operates in a common-source configuration, serving as the primary amplifying transistor, and its noise figure and input matching depend on its characteristics. M2 is in a common-gate configuration, providing reverse isolation and suppressing the Miller effect of M1. A parallel structure formed by L2, Rd, and Cd extends the output bandwidth. M3 and M4 form a source follower for the output stage, and together with M1 and M2, they create a feedforward noise cancellation structure. The biasing circuit is omitted in the diagram, with Vbias_1 and Vbias_2 representing the bias voltages.
The design focuses on achieving broadband input matching, gain optimization, and effective noise cancellation. The small signal equivalent circuit of the core amplification stage is analyzed, and the input impedance is calculated using MATLAB simulations. The results show that the input impedance remains close to 50 Ω across the 3–5 GHz band, indicating successful broadband matching. Gain analysis reveals that increasing the transconductance and load impedance can enhance the gain, but careful trade-offs must be made to maintain flatness. An inductor L3 is added to boost the gain, and the output load is designed to have a low Q value for wideband operation.
Noise cancellation is achieved through a feedback mechanism involving M3 and M4, which amplify and cancel out noise signals from the Cascode structure. Simulations confirm that increasing the inductance L4 improves high-frequency noise performance. The final design uses L4 = 616 nH, Rf = 1 kΩ, and other optimized parameters to achieve a noise figure below 2.84 dB in the 3.5–5 GHz range.
Simulation results using the SMIC 0.18 μm RF CMOS process show that the LNA consumes approximately 20.5 mW, with a maximum gain of 18 dB and an IIP3 of -12.9 dBm at 4.5 GHz. The input and output are well matched, and the reverse isolation is acceptable. These results demonstrate that the design meets the requirements for UWB systems, offering a reliable and efficient solution for future wireless communication applications.
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